1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to an architecture for improving the reliability of testing a semiconductor memory device. More particularly, the present invention relates to an architecture of a semiconductor memory device that allows external electrical detection of a current operation of a test mode during a test operation.
2. Description of the Background Art
In accordance with increase in the storage capacity and circuit complexity of a semiconductor memory device, it has become harder to avoid the production of chips with potential defect factors generated during the fabrication process at a stage prior to shipment thereof.
More specifically, there is a possibility of existence of a gate insulation film fault of an MOS transistor which is a component of the semiconductor memory device, an interlayer insulation film fault between interconnections, interconnection faults, and defects caused by particles introduced during the manufacturing process. Such a chip with these defects will become the cause of failure at the so-called "initial failure mode" if shipped directly as a product.
Thus, screening is generally carried out by the so-called "burn-in" testing. In the burn-in testing, a semiconductor memory device is operated under the condition of high temperature and high voltage to render conspicuous the above-mentioned initial defaults to eliminate faulty products prior to shipment. The time required for this burn-in testing is increased in proportion to the memory capacity even when in a simple write/read cycle. Increase in the testing time will directly result in a higher chip cost.
Increase of the testing time is suppressed by an architecture in which a plurality of semiconductor memory devices arranged on a test board are tested concurrently.
It is to be noted that a semiconductor memory device generally operates at a standard power supply voltage of 5 V to account for compatibility with the so-called TTL (Transistor-Transistor-Logic). It has become difficult to reduce the breakdown voltage and ensure reliability of a small transistor. A typical measure is to incorporate a voltage-down circuit that reduces the power supply voltage to an internal power supply voltage of 3.3 V, for example, in a semiconductor memory device with the external power supply voltage still at the level of 5 V.
In order to carry out a burn-in test for such a semiconductor memory device incorporating an internal voltage-down circuit, the operation of the internal voltage-down circuit must be interrupted and operate the internal circuitry of semiconductor memory device at the external power supply voltage. For this purpose, a particular test mode circuit is incorporated at a burn-in testing by the manufacturer, which is not used by the user side. This particular test mode circuit serves to render the operation of the semiconductor memory device to a test mode according to an external control signal. More specifically, upon sensing designation of a burn-in test mode by an external control signal, a signal is generated to suppress the operation of the internal voltage-down circuit.
This method of rendering a semiconductor memory device to a predetermined test mode by an external control signal is not limited to a burn-in test, and is carried out for other various testings.
When a plurality of semiconductor memory devices are tested concurrently in a burn-in test, each semiconductor memory device must be set to a burn-in test mode by an external control signal. If there is a semiconductor memory device that is not set to a burn-in test mode due to erroneous operation or the like, that semiconductor memory device will operate at the internal power supply voltage that is generated by the internal voltage-down circuit even if attempt is made to operate at the increased external power supply voltage. In such a state, the object of effecting accelerated testing in the burn-in test mode cannot be achieved. Therefore, reliability of the result of the burn-in testing will be degraded.
Conventionally, in a burn-in test of a semiconductor memory device including a voltage-down circuit, the difference of the power consumption of each semiconductor memory device in a normal operation and in a burn-in operation is measured to determine whether the semiconductor memory device is set to a burn-in mode or not.
For a conventional semiconductor memory device, there was no method of easily determining whether a semiconductor memory device is set to a particular test mode or not during operation of the particular test mode such as a burn-in test.
If determination according to difference in the power consumption is carried out for each semiconductor memory device, the testing time will be increased. Furthermore, the determination of whether a burn-in test mode is set or not must be appropriately monitored even during the burn-in testing. This method will further increase the testing time period, which in turn causes increase in the chip cost.